1. Fields of the Invention
The present invention relates to computer system peripheral connections. More particularly, the present invention relates to handling multiple possible interrupts in computer systems utilizing a serial peripheral interrupt bus.
2. Art Background
In the computer industry, one widely accepted system architecture for personal computers has been the AT system design. Prior systems incorporating this architecture included system buses implementing the ISA, and then later, the EISA bus protocols. This protocol defines fifteen distinct system interrupts for use by various components within the system. These interrupts are designated IRQ0 through IRQ15 with one of the IRQ signals such as IRQ2 being dedicated for use within the system's programmable interrupt controller (PIC) mechanism.
The above described computer systems that implement the ISA or EISA bus protocol interrupt mechanism generally incorporate an interrupt controller that receives the various IRQ signals and, in response thereto, provides a signal to the system's central processing unit (CPU) indicating the existence of a pending interrupt. The CPU, in response to an active interrupt signal, acknowledges the interrupt signal to the interrupt controller whereupon the interrupt controller provides a code vector to the CPU for executing the appropriate interrupt service routine (ISR). One such interrupt controller, now well known, is the Intel 8259 programmable interrupt controller (PIC). In one embodiment, that interrupt controller is capable of receiving eight distinct IRQ signals. To support the full range of IRQ signals [0:15], a first PIC receives IRQs 8-15 and generate an interrupt signal output as response thereto. The output of the first PIC is then provided as the IRQ2 input to a second PIC with the other seven inputs coming from other components. The second PIC supplies its output to the CPU. In this manner, two eight-IRQ input PICs are chained together to provide for fifteen possible IRQ signals within the system.
The above interrupt signaling protocol suffers some unfortunate disadvantages. While some computer system components are designated to provide a specific IRQ output to the system PIC, other components are left free to be configurated for multiple possible IRQ signals. Under conventional peripheral design methods, this would require a separate pin for each interrupt that the device might use, conceivably up to fifteen pins to direct 15 possible ISA IRQ interrupt signals. Each of these pins would drive a separate signal line to the system PIC for signaling the CPU when an interrupt needed to be serviced. In addition to driving up the cost of implementing peripherals, this increases the complexity and the size of the peripheral's interconnections. This has become a greater concern recently with the reduction in size of computer systems, particularly portable and notebook class systems. It is therefore an object of the present invention to reduce the pin requirements and complexity of implementing peripherals that may be configured for multiple interrupts.